The manufacture of integrated circuits (e.g., microprocessor chips) involves the testing of the manufactured parts or ICs. There are many causes of manufacturing defects in VLSI fabrication. Consequently, the parts must be tested thoroughly to detect these defects. When chips with undetected defects are shipped, and the defects are visible to the customer, these parts are returned to the manufacturer, thereby increasing the costs for the manufacturer. In this regard, it is important to minimize the number of faults in the chips prior to shipping such parts to the customer.
At the wafer level (i.e., prior to packaging), scan-based test can be employed to pre-screen the chip. If the chip fails the scan-based test, the part is discarded prior to being packaged. Unfortunately, the scan-based test is not at-speed (i.e., the test is not run at the expected clock frequency of normal chip operation). In this regard, although the scan-based test can be utilized to detect certain classes of faults, the scan-based tests are unable to detect faults that occur at-speed (i.e., frequency dependent faults).
After a chip has been packaged, a chip tester is employed to perform additional manufacturing tests at speed to detect frequency dependent faults. The chip tester applies some test method (e.g., a test case), applies inputs to the device under test, and verifies the outputs of device under test with what a test case predicts or requires. It is desirable for the test cases to provide more test coverage in less time.
The chip tester is limited in memory. In this regard, the memory has a predetermined maximum storage space that can only contain a limited number of test vectors. The challenge for the test engineer is to maximize the amount of fault coverage within a minimum amount of memory space. These manufacturing tests typically include a suite of test cases that are executed by the tester. The manufactured parts are subjected to these manufacturing tests in order to screen for defective parts.
Manufacturing tests are designed to detect manufacturing defects, which can be modeled in various ways. For example, many of these manufacturing tests are designed to detect faults that are modeled as “stuck-at-faults”. A stuck-at-fault is a node in the circuit that due to errors in the manufacturing process is “stuck” at a particular voltage (e.g., either a logic high or logic low state). This error can occur, for example, due to two wires being shorted together or a node being shorted to power or ground. Without the error, the particular node should feature a voltage that varies depending on the output of a preceding circuit element.
In order to detect these faults, a test case must accomplish two tasks. First, the test case must activate the fault (i.e., set up the condition that causes the fault to occur). Second, the test case must propagate the fault so that it can be observed at an external pin of the integrated circuit.
There are generally two prior art approaches for generating at-speed manufacturing test cases. In a first approach, a test engineer manually writes the manufacturing test cases from scratch. The test engineer writes separate tests for the different functional blocks that need to be tested. Often this process is an iterative one, where the test case is refined and modified to effectively identify as many faults for a particular functional block. As can be appreciated, this approach is time-consuming and resource intensive.
In a second approach, the manufacturing test cases are manually written based on design verification test cases, which are intended to validate the design of the integrated circuit prior to manufacture thereof. Test cases are designed to test a particular functional unit of the processor. For example, a set of test cases can be designed to test the operation of the floating point unit. Another set of test cases can be designed to test the cache.
One disadvantage of this approach is that the manual selection of appropriate test cases from the millions of design verification test cases (DVTCs) that are available is a difficult and time-consuming process.
A second disadvantage is that since these test cases were not written for manufacture testing, there is no code to ensure that faults are propagated to the chip periphery (e.g., pins) to make the faults observable to the tester. As noted previously, the effectiveness of a test case depends on whether the fault is observable (i.e., whether the fault propagated to the pins of the chip so that the fault can be detected). Writing code to make a fault observable on a pin of the chip under test is a time-consuming and effort intensive process.
Furthermore, the design verification test cases typically include initialization of registers, internal nodes, etc., some of which are not needed for manufacturing testing. When the design verification test cases are converted into manufacturing tests, the unnecessary initialization translates into long sequences of instructions (e.g., diagnose instructions) that set up the initial conditions of the test case so that a targeted fault can be exercised.
In the simulation environment of design verification test cases, there is no cost for initialization since the state of internal nodes can be affected without using instruction sequences. However, in the environment of a manufacturing test the initialization of the state of some internal nodes is often difficult, sometimes not possible, unnecessary, and costly (i.e., requiring many initialization instructions or a sequence of instructions). Although these initial conditions (also referred to as initial state) may be important for design verification, often many of the initial conditions are not necessary to activate the faults relevant to manufacture testing and manufacture detects. Furthermore, the extra code for initialization decreases the throughput of chips through the testers and requires that the tester have a larger amount of fast memory to hold the test cases.
Moreover, the DVTC may over specify the initializations. For example, a DVTC may specify a particular entry in a translation look aside buffer (TLB) in which a particular translation should be initialized. While this may be important for pre-silicon verification, a manufacturing test may not rely on which entry contains a translation, but simply requires that a translation be present in the TLB. The code required to place a translation in a particular entry in the TLB may be more involved and lengthier than code to initialize that particular translation regardless of location.
As the complexity of the integrated circuit increases, the difficulty of generating manufacturing test cases becomes more pronounced. For example, when a processor design features several different levels of internal cache, the length of code required to set up the initial state of the processor increases and promoting activated faults to the pins of the chip for observation becomes more difficult.
Based on the foregoing, there remains a need for an automatic manufacturing test case generation method and system that overcomes the disadvantages of the prior art.